In this position, you will be a key member of the mixed-signal and/or analog circuit design team in the Advanced Platform Operations (APO). Responsible for back-end level analysis of I/O circuits: digital functionality (RTL coding and simulation), timing analysis, noise sensitivity, Formal Equivalence Verification (FEV) and Reliability Verification (RV). Driving the development (collaterals and/or capabilities) and deployment of next-generation high-speed serial I/O links, such as QPI, SMI, PCI-e, and also DDR.