Sr. PLL Design Engineer - 1705
Sunnyvale, CA
Job Description:
You will be responsible for the architecture, design, modeling, trade-off analysis, implementation, verification, support, & test development of medium & high performance, fractional-N PLLs & low-power integer-N in a variety of CMOS process technologies for RF & timing applications.
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Sr. PLL Design Engineer - 1705
Sunnyvale, CA
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