We are looking for logic design engineers who have experience with RTL coding, RTL validation, synthesis, and timing closure. The System-On-a-Chip Enabling Group (SEG) provides IP building blocks that other teams integrate into their products. Primary areas of experience include developing logic architecture specs and implementing logic for high-speed digital logic; general knowledge of logic architectures related to PHY's; and ability to code efficient high speed logic designs (up to 4 GHz).